1. Field of the Invention
The present invention relates to a method for producing a metal structure in a semiconductor substrate, the front side of which is provided with a layer structure.
2. Description of the Related Art
This method is suited in particular for implementing low-resistance vias in an ASIC or MEMS component and in cap wafers for such components. With the aid of the method in question it is also possible, however, to produce other metal structures in a semiconductor substrate, such as plate capacitors or cylindrical capacitors and coil arrangements.
The background of the subject matter for the present invention is provided in published European patent application document EP 2 408 006 A2. This publication describes a method for producing a metallic via which is electrically insulated from the adjacent semiconductor substrate by a circumferential air gap. According to EP 2 408 006 A2 a ring-shaped isolation trench is initially produced for this purpose which extends over the entire thickness of the substrate. For this purpose a trench mask having a lattice structure is used which is laterally undercut during the trench process in such a way that a continuous trench-like ditch forms in the area below the lattice structure. A dielectric material is then deposited over the lattice structure, which is also deposited on the walls of the ditch. In the process, the isolation trench is superficially sealed leaving behind an air gap in the trench-like ditch. Only then is a through-opening produced within the substrate region surrounded by the isolation trench and filled with metal.
This approach proves to be problematic in several respects. The merely superficially sealed isolation trench with the enclosed air gap is relatively sensitive to mechanical forces. This must be taken into account during later processing and, in particular, when filling the through-opening with metal. A screen printing technique, for example, should not be used in this case since the sealing layer over the isolation trench could be damaged or even destroyed by pressing on the screen. Thus, in the known method for producing a via, a filling method must be selected which is compatible with the fragile structure of the sealing layer over the circumferential isolation trench. A planarization of the rear side of the semiconductor substrate after filling the through-opening is also problematic due to the sensitivity of the via with the circumferential isolation trench. This in turn makes handling difficult during a subsequent processing of the front side of the semiconductor substrate.
Moreover, notching effects may appear when producing the circumferential isolation trench and when producing the through-opening, in particular at a high aspect ratio, since no lateral etch stop is provided in conjunction with the known method for producing a via. The resulting lateral expansion in the bottom area of the circumferential isolation trench and/or the through-opening may impair the connection contact of the via.